FPGA IP Cores and Hardware
// FPGA IP Cores:
Phase Synchronisation & Monitoring Module
Field of application: High-speed communication systems (high-speed transceivers/SERDES subsystems), optical communication. The module ensures that the data received by high-speed optical communication systems is accurate and properly synchronized.
It compares a known pattern (synchronisation marker) with the data stream received, adjusting the starting point of the comparison and finding the best match. A configurable threshold can be set to account for possible errors. The accuracy of synchronisation with the data stream process can influence the received data’s final Bit Error Rate (BER) and overall ranging accuracy (if used for telemetry ranging purposes).
The Phase Monitor module can be used as the downlink or uplink data synchroniser for both the Ground Station and Spacecraft subsystems.
// FPGA IP Cores:
Time-to-Digital
Conversion
Field of application: Systems utilising time-tagging and coincidence detection for applications such as Quantum Key Distribution and Quantum Information Networks in space. Time-to-Digital Conversion (TDC) IP Core offers better than 5 picoseconds accuracy for time-tagging and single photon detection.
It can be implemented on a rad-hard RTG4 FPGA device, ensuring reliable performance for your project. Engineered for systems that demand high precision and reliability, it enhances detection rates and enables more efficient quantum key generation. It combines coarse and fine time measurements, making it a scalable, high-performance solution for demanding quantum and time-tagging systems.
// FPGA IP Cores:
Low-level Stepper Motor Controller
Field of application: Antenna pointing mechanisms, payload rotation mechanisms, pointing and tracking applications or any application where precise movement of mechanisms is required. The SMC (Stepper Motor Controller) IP Core allows precise stepper motor movement.
Its essential feature is the ability to perform immediate trajectory recalculation upon receiving a new position or velocity during an ongoing movement. It offers precise movement control and real-time parameter updates during motion. It was successfully implemented in a high-stakes ESA space mission, delivering reliable results.
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// FPGA IP Cores:
Interface to ModBus
Field of application: FPGA designers who require a verified yet simple and technology-independent solution to provide MODBUS Remote Terminal Unit (RTU) protocol-based communication in their project. The MODBUS RTU interface IP Core enables efficient communication across FPGA systems.
It supports two UART (Universal Asynchronous Receiver-Transmitter) channels to ensure redundancy and robust performance. The system includes real-time diagnostics to monitor system health and built-in data integrity checks using CRC (Cyclic Redundancy Check). It is written in VHDL, which allows swift adaptation to different FPGAs. This IP core has been successfully used in space projects, demonstrating its reliability and flexibility for secure and precise data transfer.
// HARDWARE
Coincidence Detector Module
Field of application: universities, particle laboratories, cosmic ray experiments, interactive physics demonstrations, photonics experiments, etc. The coincidence detector is a low-cost, easy-to-integrate module with a configurable detection window (from ±65 ps (100% detection rate) – up to ±4 ns) and built-in self-test capabilities;
It also has two inputs (SMA connectors) that accept NIM (Nuclear Instrumentation Module) or TTL (Transistor-Transistor Logic) signals. The output in the LVTTL (Low-Voltage Transistor-Transistor Logic) standard toggles its state whenever a coincidence is detected, making integration with the acquisition system easier. The device can detect up to 275 million coincidences per second.
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